WO2002083522A1 - Separateurs presentant des elements amortisseurs et destines a des plaquettes pour circuits integres - Google Patents

Separateurs presentant des elements amortisseurs et destines a des plaquettes pour circuits integres Download PDF

Info

Publication number
WO2002083522A1
WO2002083522A1 PCT/US2002/010403 US0210403W WO02083522A1 WO 2002083522 A1 WO2002083522 A1 WO 2002083522A1 US 0210403 W US0210403 W US 0210403W WO 02083522 A1 WO02083522 A1 WO 02083522A1
Authority
WO
WIPO (PCT)
Prior art keywords
wafers
film
wafer
projections
bump pads
Prior art date
Application number
PCT/US2002/010403
Other languages
English (en)
Inventor
Ray G. Brooks
Timothy W. Brooks
Original Assignee
Brooks Ray G
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Brooks Ray G filed Critical Brooks Ray G
Publication of WO2002083522A1 publication Critical patent/WO2002083522A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67356—Closed carriers specially adapted for containing chips, dies or ICs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/673—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere using specially adapted carriers or holders; Fixing the workpieces on such carriers or holders
    • H01L21/6735—Closed carriers
    • H01L21/67369—Closed carriers characterised by shock absorbing elements, e.g. retainers or cushions

Definitions

  • the present invention relates to a method and apparatus for protecting sensitive articles, such as integrated circuits, from mechanical shock.
  • bond pads are fabricated in the shape of a ball for the purpose of accommodating "pick & place” operations on Printed Circuit (PC) boards. These balls are normally made of PbSn solder having diameters in the micrometer range.
  • bond pads fabricated with solder balls are hereinafter referred to as “bump bond pads” or “bump pads” and the IC wafers having them are referred to as “bumped wafers”. This is because the bump pads have elevated heights that are different from wafer surfaces.
  • shock energy is mechanical in nature and can occur when the shipping container of IC wafers is mishandled, such as when the container is dropped, bumped, or otherwise jarred.
  • the wafers are also subject to damage due to stress energy. Stress damage occurs, for example, when the wafers are tightly packed within the shipping containers or even from the combined weight of the packaged wafers. To prevent wafer damage, shock energy must be absorbed and stress energy must be relieved.
  • shock/stress energy becomes accentuated and enhanced with the height of the bump pads.
  • the mechanical impact or stress of one wafer against an adjoining wafer is concentrated at the bump pads instead of being evenly distributed over the entire surface area of the wafer. Consequently, in the absence of a proper cushioning scheme, this enhanced energy can extrapolate to catastrophic energy to damage IC wafers when "coin-stacked" on top of each other within containers.
  • a third example would be prior art wafer shipping container made of exceptionally thin walls with little ability to absorb shock or stress energy that can easily become in excess of the ability of enclosed cushions to absorb and this can damage wafers.
  • any shock or stress energy caused by a sudden impact or mishandling that exceeds the cushions' ability to absorb can transfer damage to: (1) exceptionally thin wafers coin-stacked within any or all of the above described shipping containers, and (2) wafers having bump pads "coin-stacked" within any or all of the above described shipping containers.
  • IC wafers stacked within shipping containers are separated from adjacent wafers by sheets of material known as separators or interleafs.
  • Prior art interleafs are made of various materials including sheets of polyethylene fiber (e.g. Tyvek), polymer films, rice paper, etc., and all, by the nature of their structure, have little or no resiliency to absorb any damaging energy. These interleafs are only designed to separate IC wafers from each other without cushioning qualities. Therefore, prior art interleafs, regardless of make or type, will have little or no resiliency, and thus no ability to absorb damaging shock/stress energy to protect wafers stored within containers that exceed the ability of enclosed cushions to absorb.
  • foam separators that are made of foam do have resiliency through the thickness of the separator and will adequately provide shock protection for wafers with bump pads by absorbing the shock energy.
  • foam separators have chemical additives to achieve surface resistivities of 10 4 - 10 n ohms in order to prevent electrostatic discharge (ESD) and electrical overstress (EOS) events.
  • ESD electrostatic discharge
  • EOS electrical overstress
  • foam separators are also unnecessarily thick and take up space and leave each and every bump pad subject to corrosive damage caused by chemical depletion or outgassing of airborne molecular contaminants (AMCs).
  • AMCs airborne molecular contaminants
  • the present invention provides a packaging configuration for integrated circuit wafers.
  • a film having a pattern of projections extending from the film is interposed between the two wafers which are stacked.
  • the projections are independent from one another and absorb mechanical shock applied to the wafers.
  • the film has a dissipative layer and an insulating layer, with the dissipative layer of the film having a surface resistance of between 1 X 10 4 - 1 X 10 11 ohms.
  • the insulating layer of the film is in contact with a circuit side of one of the adjacent wafers.
  • the wafers comprise bump pads, with the film contacting the bump pads of at least one of the wafers.
  • the film projections comprise bosses.
  • the present invention also provides a system for providing protection to integrated circuit wafers.
  • a container has an interior space for receiving the wafers. At least two of the wafers are stacked inside of the interior space.
  • the film has a pattern of projections extending from the film, with the film being interposed between the two wafers. The projections are independent from one another and absorb mechanical shock applied to the wafers.
  • the film has a dissipative layer and an insulating layer, with the dissipative layer of the film having a surface resistance of between 1 X 10 4 - 1 X 10 11 ohms.
  • the insulating layer of the film is in contact with a circuit side of one of the adjacent wafers.
  • the wafers comprises bump pads, with the film contacting the bump pads of at least one of the wafers.
  • the film projections comprise bosses.
  • Fig. 1 is an exploded isometric view of a shipping container showing wafers in a coin-stacked configuration, with the separator of the present invention, in accordance with a preferred embodiment.
  • Fig. 2 is a cross-sectional view taken through lines II-II of Fig. 1.
  • This invention specifies an interleaf or separator especially designed for the purpose of separating and simultaneously protecting the thin IC wafers and/or wafers having bump bond pads from sudden damage caused by shock energy generally perpetuated by a sudden impact during shipment phases or by stresses caused by mishandling during packaging process prior to shipment phases.
  • regular IC wafers are more difficult to damage because they are sufficiently thick in structure and have flat bond pads by which to withstand a resonance of shock/stress energy that might occur during handling, packaging and shipment phases. Wafers with thin substrates will easily break if exposed to shock/stress energy, and wafers with bump bond pads will become instruments to transfer shock/stress energy to the next wafer to cause breakage.
  • the interleaf invention is designed with a series of bumps.
  • the interleafs are co-extruded from polymer resins having a matrix of either carbon or copper with a surface resistivity ranging from 10 5 to 10 ⁇ to avoid ESD events.
  • the interleafs are designed to receive and absorb excessive shock/stress energy not absorbed by the cushions assigned to shipping containers.
  • these bumps are impressions elevated on one side of the separator and each has a given height with a given distance from each other, thus effecting a cushioning system.
  • each separator having bumps has the unique feature to separate each and every wafer from each other while providing a cushioning system for each and every wafer within shipping container against shock/stress energy during handling, packaging and shipment phases.
  • Fig. 1 there is shown an exploded isometric view of an IC wafer shipping container 11, having top and bottom covers 13, 15. Top and bottom cushions 17, 19 are also provided inside of the top and bottom covers 13, 15. IC wafers 21 are stacked between the cushions 17, 19. The wafers 21 are coin-stacked. As shown in Fig. 2, at least one side of each wafer has bump pads 23 thereon.
  • the separator 25 prevent the wafers 21 from contacting each other.
  • the separator 23 of the present invention is cushioned to prevent damage, both shock and chemical, to IC wafers having bump pads.
  • the separators are made of relatively AMC free plastic films that provide wafers with protection from stress and/or shock energy in the same resilient manner as those separators that are made of foam.
  • This invention has the means to establish protection from stress and/or shock energy that transfers damage to wafers while simultaneously preventing: (1) corrosive damage to bump pads caused by chemical depletion or outgassing and (2) ESD and EOS electrical damage caused by improper surface resistivity of ⁇ 10 4 ohms and >10 ⁇ ohms.
  • the means within this invention that enhances the quality of wafer separation during the shipping phase is a plurality of embossed bumps 27 or bosses.
  • Each boss 27 specifically provides: (1) a cavity 31 that isolates bump pads from stress and/or shock energy that damages wafers and (2) a means to absorb stress and/or shock energy for those bump pads 23 that can transfer damage to wafers, which means is in the form of the void 33 or space between bosses.
  • this invention provides IC wafers with bump pads (solder balls with height) a means to either absorb or isolate stress and/or shock energy that damages wafers.
  • the separator 25 is embossed, not with lines, but with bosses 27 that serve as standoffs.
  • these bosses are circular.
  • the embossed bosses 27 can be any shape.
  • the bosses are spaced together so as to provide support for the separator spanning between the bosses.
  • the bosses 27 are independent of one another so that mechanical shock by one boss is not transmitted to other bosses.
  • This invention provides an even greater solution when cushioned copperleaf separators are chosen for packaging wafers within containers for shipment. Unlike no other, copperleafs are sacrificial in that they absorb ionic contaminants and become a cleaning machine that assures packaged wafers arrive at the customer's location in a pristine condition. Such separators 25 are impregnated with copper instead of carbon.
  • the separators 25 are made from a film.
  • the film has two layers, namely a dissipative layer and an insulating (or insulative) layer.
  • the dissipative layer is polyethylene with carbon (or copper); the carbon serves to dissipate electrical charges.
  • the insulating layer is polyethylene, which is a low density type of polyethylene; however it is also believed that medium and high density polyethylenes will also be satisfactory.
  • the dissipative layer has a sufficient amount of carbon therein so that the surface resistance of the dissipative layer is between 1 x 10 4 to 1 x 10 u ohms, as measured by the ESD association test method SI 1.11.
  • the thickness of the insulating layer is 0.25 mils or less.
  • the thickness of the dissipative layer can vary. We have found that thicknesses of 3, 5 and 9 mils work well. However, other thicknesses, either smaller or greater, will also likely work well depending on the particular application.
  • a polyethylene with carbon and a polyethylene without carbon are extruded into separate layers. The two layers, being extruded together, are coupled together and form the film. The film can likely be made by other processes, such as laminating and coating.
  • the embossing is done from the insulating layer to the dissipative layer.
  • the film is described in our earlier U.S. Patent No. 6,286,684, the disclosures of which is incorporated by reference. That patent teaches that the film is embossed with a grid to minimize the film separators from sticking to each other.
  • the embossing is a grid and thus does not create independent bosses. Mechanical shock carried by one part of the grid will be transmitted to other parts of the grid.
  • the separator 25 is the film cut into a circular shape to match the shape of the IC wafer 21.
  • the separator 25 has a diameter that is slightly larger than the diameter of the particular IC wafers 21.
  • Each wafer 21 has a circuit side and an opposite or grind side.
  • the bump pads 23 are located on the circuit side of the wafer.
  • separators 25 are placed between the wafers 21.
  • the insulating layer of the separator 25 is located in contact with the circuit side (the bump pad side) of the wafer.
  • the dissipative layer is located in contact with the grind (or other) side of the next adjacent wafer. Thus, the insulating layer is interposed between the sensitive circuits and the dissipative layer.
  • a stack of wafers and the separators is formed and placed into the container. The wafers contact only the separators and not other wafers.
  • the film bosses 27 serve as standoff areas.
  • the embossing provides shock absorption.
  • the resilient bosses provide cushioning and prevent wafer damage.
  • the height of the bosses 27 from the film is preferably greater than the height of the wafer bump pads 23. The greater the height of the bosses 27 relative to the height of the wafer bump pads 23, the greater the spacing between the bosses.
  • bosses 27 are likewise flexible.
  • the bosses provide a resiliency that allows the absorption of shock.
  • the bump pads 23 located adjacent to a void 31 caused by a boss are not in contact with any solid object. Thus, during a mechanical shock, these bump pads are physically isolated from contacting any object.
  • the bump pads that are between bosses are in contact with the separator 25, but these portions of the separator are backed by voids 33. Thus, the bosses will flex under mechanical shock and the bump pads and separator will move in and out of the voids.
  • the dissipative layer is made dissipative by the presence of carbon in the polymer.
  • the dissipative layer presents a high resistance path to ground. Any static charge which accumulates on an adjacent article dissipates into the dissipative layer. Because the resistance of the dissipative layer is between 1 x 10 4 to 1 x 10 11 ohms, the charge dissipates in a controlled manner so as not to damage the article.
  • the insulating layer protects the article from the carbon. If the article was in direct contact with the dissipative layer, then carbon particles can be sloughed off and remain in contact with the articles. Having such dissipative particles in contact with sensitive articles, such as integrated circuits, is an undesirable contamination. The insulating layer prevents this sloughing of carbon (or other dissipative) particles onto the wafer.
  • the insulating layer is configured so as to allow static discharges to pass therethrough.
  • the insulating layer which is a polymer, has myriad microscopic channels therethrough, which channels can serve as paths for static discharges.
  • Polymers typically have some porosity which is a function of the type of polymer, the thickness of the polymer and the particular material which is able to penetrate the polymer. An example of such porosity can be measured as the moisture vapor transmission rate (MVTR). Molecules of water vapor can penetrate some polymer layers. The penetration is possible because the polymer layer has a myriad of microscopic paths for the vapor molecules to follow through the layer.
  • the possibility of contaminating the wafers 21 by the separators 25 is minimized by the bosses 27.
  • the bosses 27 minimize physical contact between the separator 25 and the wafer 21. Much of the wafer surface will not be in contact with the separator, instead being located either in the void 31 inside of the bosses 27 or in the spaces 33 between the bosses.
  • the separators 25 can be oriented as shown in Fig. 2, wherein the surface area contact between the separator and the wafer is minimized on the side of the wafer opposite the bump pads, or the separators can be oriented in a reverse manner, wherein the surface area contact between a separator and a wafer is minimized on the bump pad side of the wafer.

Abstract

L'invention concerne un contenant de transport (11), destiné à des plaquettes pour circuits intégrés, contenant une pile de plaquettes (21). Au moins une face de chaque plaquette (21) présente des bosses de connexion conductrices (23). Un séparateur (25) est placé entre deux plaquettes. Ces séparateurs sous forme de films présentent chacun une couche dissipative et une couche isolante, et comportent des éléments amortisseurs sous forme de bosses (27) pour protéger les plaquettes contre les chocs mécaniques et électriques.
PCT/US2002/010403 2001-04-10 2002-04-01 Separateurs presentant des elements amortisseurs et destines a des plaquettes pour circuits integres WO2002083522A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28281601P 2001-04-10 2001-04-10
US60/282,816 2001-04-10

Publications (1)

Publication Number Publication Date
WO2002083522A1 true WO2002083522A1 (fr) 2002-10-24

Family

ID=23083240

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2002/010403 WO2002083522A1 (fr) 2001-04-10 2002-04-01 Separateurs presentant des elements amortisseurs et destines a des plaquettes pour circuits integres

Country Status (2)

Country Link
US (1) US20020144927A1 (fr)
WO (1) WO2002083522A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2178114A3 (fr) * 2008-10-14 2011-11-23 Christian Senning Verpackungsmaschinen GmbH & Co. Emballages pour produits fins plats en forme de disques

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7425362B2 (en) * 2002-09-06 2008-09-16 E.Pak International, Inc. Plastic packaging cushion
US20060105498A1 (en) * 2004-08-13 2006-05-18 Cheng-Chung Huang Wafer stack separator
KR100640957B1 (ko) * 2004-12-30 2006-11-02 동부일렉트로닉스 주식회사 이미지센서 웨이퍼 운송기구
JP2006282278A (ja) * 2005-03-10 2006-10-19 Epson Toyocom Corp ウェハー用梱包体
US20070068846A1 (en) * 2005-09-29 2007-03-29 Huang-Ting Hsiao Wafer packing
JP4947631B2 (ja) * 2006-07-19 2012-06-06 ミライアル株式会社 クッションシート付ウエハ収納容器
DE112007001758T5 (de) * 2006-07-25 2009-09-17 Miraial Co., Ltd. Wafer-Behälter mit Polsterfolien
JP4883627B2 (ja) 2007-01-24 2012-02-22 ミライアル株式会社 クッションシート付ウエハ収納容器
US8863956B2 (en) * 2011-01-19 2014-10-21 Ray G. Brooks Packaging system for protection of IC wafers during fabrication, transport and storage
US9653331B2 (en) * 2011-02-16 2017-05-16 Texchem Advanced Products Incorporated Sdn. Bhd. Single and dual stage wafer cushion
US9224627B2 (en) 2011-02-16 2015-12-29 Texchem Advanced Products Incorporated Sdn Bhd Single and dual stage wafer cushion and wafer separator
JP5976307B2 (ja) * 2011-12-06 2016-08-23 アキレス株式会社 ウェーハ保護クッション材の製造方法
US20130173039A1 (en) * 2012-01-04 2013-07-04 Seagate Technology Llc Methods and devices for determining a teaching point location using pressure measurements
CN102582961B (zh) * 2012-03-06 2014-01-01 深圳市华星光电技术有限公司 一种便于吸盘吸附拿取的缓冲片材和玻璃转运包
US20150076029A1 (en) * 2013-09-19 2015-03-19 International Business Machines Corporation Package assembly for thin wafer shipping
JP6617433B2 (ja) * 2015-04-17 2019-12-11 日本電気硝子株式会社 ガラス基板梱包体
JP2017183448A (ja) * 2016-03-30 2017-10-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US11442370B2 (en) * 2019-10-16 2022-09-13 Gudeng Precision Industrial Co., Ltd Reticle retaining system
DE102020130292A1 (de) 2020-11-17 2022-05-19 Schott Ag Verfahren zum Verpacken und Entpacken flächiger Substrate sowie Verpackung für flächige Substrate

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226372A (en) * 1989-02-13 1993-07-13 Coors Brewing Company Slip pallet with a cushioning effect
US5366079A (en) * 1993-08-19 1994-11-22 Taiwan Semiconductor Manufacturing Company Integrated circuit wafer and retainer element combination
US5699916A (en) * 1997-02-03 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd. Integrated circuit wafer container
US6193068B1 (en) * 1998-05-07 2001-02-27 Texas Instruments Incorporated Containment device for retaining semiconductor wafers

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5226372A (en) * 1989-02-13 1993-07-13 Coors Brewing Company Slip pallet with a cushioning effect
US5366079A (en) * 1993-08-19 1994-11-22 Taiwan Semiconductor Manufacturing Company Integrated circuit wafer and retainer element combination
US5699916A (en) * 1997-02-03 1997-12-23 Taiwan Semiconductor Manufacturing Company Ltd. Integrated circuit wafer container
US6193068B1 (en) * 1998-05-07 2001-02-27 Texas Instruments Incorporated Containment device for retaining semiconductor wafers

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2178114A3 (fr) * 2008-10-14 2011-11-23 Christian Senning Verpackungsmaschinen GmbH & Co. Emballages pour produits fins plats en forme de disques

Also Published As

Publication number Publication date
US20020144927A1 (en) 2002-10-10

Similar Documents

Publication Publication Date Title
US20020144927A1 (en) IC wafer cushioned separators
US6286684B1 (en) Protective system for integrated circuit (IC) wafers retained within containers designed for storage and shipment
KR100446842B1 (ko) 반도체웨이퍼의수납용기,수납구조및수납.인출방법
NO306938B1 (no) Stive flerlags anti-statiske pakkematerialer samt beholder som omfatter samme
US8863956B2 (en) Packaging system for protection of IC wafers during fabrication, transport and storage
US5613610A (en) Naturally degradable and recyclable static-dissipative packaging material
KR100966985B1 (ko) 전자 부품 포장용 커버 테이프 및 전자 부품 포장체
KR20060007387A (ko) 전자부품 테이프-포장용 커버 테이프
US6029427A (en) Method and apparatus for handling semiconductor chips
US5014849A (en) Electro-static protective container for electrical components
JP4329536B2 (ja) 半導体ウェハーの収納具
US5090563A (en) Electro-static protective container for electrical components
EP0470920B1 (fr) Tube pour modules à réseau de broches
JP6545601B2 (ja) セパレータ
US20060011509A1 (en) Packaging system and method for storing electronic components
US7237606B2 (en) Wafer supporter
US20060105498A1 (en) Wafer stack separator
US6540086B1 (en) Protective cover tape having a foam layer
JP6806753B2 (ja) カバーテープおよび電子部品用包装体
WO2004024594A1 (fr) Support a surfaces adhesives
JP2004269056A (ja) 調節可能な厚さを有する包装用プラットフォーム
US20070272590A1 (en) Packaging structure
KR101951229B1 (ko) 반도체 패키지의 볼면 척킹을 위한 정전척
EP3840029B1 (fr) Empilage de réseaux et de corps de séparateur pendant le traitement de porteuses de composantes sur le niveau de réseau
US20080013247A1 (en) Anti-static pallet

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE TR

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP

WWW Wipo information: withdrawn in national office

Country of ref document: JP